RV32I RISC-V CPU
5 stage pipelined RISC-V core in SystemVerilog that runs compiled C from BRAM on a Tang Nano 20K FPGA.
RepoI mostly build embedded systems and hardware: FPGAs, PCBs, and the software that runs on them.
5 stage pipelined RISC-V core in SystemVerilog that runs compiled C from BRAM on a Tang Nano 20K FPGA.
RepoBare metal, STM32U5 based ECG & SCG wearable. Captures and analyzes the signals in real time and produces on device HRV metrics. >98% beat detection accuracy
RepoA passive, privacy respecting, travel journal for iPhone. Automatically tracks your location in the background and turns it into places, trips, and an exploration map made of hexagons that fills in over time. Powered by on device Foundation Models.